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1 data sheet acquired from harris semiconductor schs195c features simultaneous and independent read and write operations expandable to 512 words of n-bits three-state outputs organized as 4 words x 4 bits wide buffered inputs typical read time = 16ns for ?c670 v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. read and write address and enable inputs allow simultaneous writing into one location while reading another. four data inputs are provided to store the 4-bit word. the write address inputs (wa0 and wa1) determine the location of the stored word in the register. when write enable ( we) is low the word is entered into the address location and it remains transparent to the data. the outputs will reflect the true form of the input data. when ( we) is high data and address inputs are inhibited. data acquisition from the four registers is made possible by the read address inputs (ra1 and ra0). the addressed word appears at the output when the read enable ( re) is low. the output is in the high impedance state when the ( re) is high. outputs can be tied together to increase the word capacity to 512 x 4 bits. pinout cd54hc670 (cerdip) cd74hc670, CD74HCT670 (pdip, soic) top view ordering information part number temp. range ( o c) package cd54hc670f3a -55 to 125 16 ld cerdip cd74hc670e -55 to 125 16 ld pdip cd74hc670m -55 to 125 16 ld soic cd74hc670mt -55 to 125 16 ld soic cd74hc670m96 -55 to 125 16 ld soic CD74HCT670e -55 to 125 16 ld pdip CD74HCT670m -55 to 125 16 ld soic CD74HCT670mt -55 to 125 16 ld soic CD74HCT670m96 -55 to 125 16 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 d1 d2 d3 ra1 ra0 q3 gnd q2 v cc wa0 wa1 we re q0 q1 d0 january 1998 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc670, cd74hc670, CD74HCT670 high-speed cmos logic 4x4 register file [ /title ( cd74h c 670, c d74h c t670) / subject ( high- s peed c mos l ogic 4 x4 reg- i ster
2 functional diagram 9 6 7 10 q0 q1 q2 q3 4 11 15 1 3 d0 d2 we re 514 13 ra1 ra0 wa0 wa1 12 2 d1 d3 write mode select table operating mode inputs internal latches (note 1) we d n write data l l l lhh data latched h x no change note: 1. the write address (wa0 and wa1) to the ?nternal latches must be stable while we is low for conventional operation. read mode select table operating mode inputs output q n re internal latches (note 2) read l l l lhh disabled h x (z) note: 2. the selection of the ?nternal latches by read address (ra0 and ra1) are not constrained by we or re operation. h = high voltage level l = low voltage level x= don? care z = high impedance ?ff?state cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc drain current, per output, i o for -0.5v < v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . . . . . 35ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc . . . . . . . . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range, t a . . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 3. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -6 4.5 3.98 - - 3.84 - 3.7 - v -7.8 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 6 4.5 - - 0.26 - 0.33 - 0.4 v 7.8 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
4 quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a three- state leakage current v il or v ih v o = v cc or gnd 6-- 0.5 - 5.0 - 10 a hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -6 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 6 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 a three- state leakage current v il or v ih v o = v cc or gnd 5.5 - - 0.5 - 5.0 - 10 a additional quiescent device current per input pin: 1 unit load ? i cc (note 4) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads we 0.3 wa0 0.2 wa1 0.4 re 1.5 data 0.15 ra0 0.4 ra1 0.7 note: unit load is ? i cc limit speci? in dc electrical speci?ations table, e.g., 360 a max. at 25 o c. cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
5 prerequisite for switching speci?ations parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min typ max min typ max hc types setup time data to we write to we t su , t h 260- -75- -90- -ns 4.5 12 - - 15 - - 18 - - ns 610- -13- -15- -ns hold time data to we write to we t h , t w 25--5- -5--ns 4.5 5 - - 5 - - 5 - - ns 65--5- -5--ns pulse width we t w 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 614- -17- -20- -ns latch time we to ra0, ra1 t latch 2 100 - - 125 - - 150 - - ns 4.5 20 - - 25 - - 30 - - ns 617- -21- -26- -ns hct types setup time data to we t su , t h 4.5 12 - - 15 - - 18 - - ns hold time data to we write to we t h , t w 4.5 5 - - 5 - - 5 - - ns setup time write to we t su 4.5 18 - - 23 - - 27 - - ns pulse width we t w 4.5 20 - - 25 - - 30 - - ns latch time we to ra0, ra1 t latch 4.5 25 - - 31 - - 38 - - ns switching speci?ations c l = 50pf, input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh , t phl c l = 50pf reading any word 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 49 - 59 ns c l = 15pf 5 - 16 - - - - - ns c l = 50pf 6 - - 33 - 42 - 50 ns write enable to output t plh ,t phl c l = 50pf 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns c l = 50pf 6 - - 43 - 54 - 64 ns cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
6 data to output t plh ,t phl c l = 50pf 2 - - 256 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns c l = 50pf 6 - - 43 - 54 - 64 ns output disable time t plz ,t phz c l = 50pf 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - - - - - ns c l = 50pf 6 - - 26 - 33 - 38 ns output enable time t pzl ,t pzh c l = 50pf 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 12 - - - - - ns c l = 50pf 6 - - 26 - 33 - 38 ns output transition time t thl , t tlh c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 10 - 19 ns input capacitance c i c l = 50pf - 10 - 10 - 10 - 10 pf three-state output capacitance c o - - 20 - 20 - 20 - 20 pf power dissipation capacitance (notes 5, 6) c pd c l = 15pf 5 - 59 - - - - - pf hct types propagation delay t phl, t plh reading any word c l = 50pf 4.5 - - 40 - 50 - 53 ns c l = 15pf 5 - 17 - - - - - ns write enable to output t phl, t plh c l = 50pf 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns data to output t phl, t plh c l = 50pf 4.5 - - 50 - 63 - 75 ns c l = 15pf 5 - 21 - - - - - ns output disable time t plz ,t phz c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - - - - - ns output enable time t pzl ,t pzh c l = 50pf 4.5 - - 38 - 48 - 57 ns c l = 15pf 5 - 16 - - - - - ns output transition time t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns input capacitance c i c l = 50pf - 10 - 10 - 10 - 10 pf three-state output capacitance c o - - 20 - 20 - 20 - 20 pf power dissipation capacitance (notes 5, 6) c pd c l = 15pf 5 - 66 - - - - - pf notes: 5. c pd is used to determine the dynamic power consumption, per output. 6. p d =c pd v cc 2 f i + c l v cc 2 f o where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations c l = 50pf, input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max cd54hc670, cd74hc670, CD74HCT670
7 test circuits and waveforms note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 1. hc clock pulse rise and fall times and pulse width note: outputs should be switching from 10% v cc to 90% v cc in accordance with device truth table. for f max , input duty cycle = 50%. figure 2. hct clock pulse rise and fall times and pulse width figure 3. hc transition times and propagation delay times, combination logic figure 4. hct transition times and propagation delay times, combination logic figure 5. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 6. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits clock 90% 50% 10% gnd v cc t r c l t f c l 50% 50% t wl t wh 10% t wl + t wh = fc l i clock 2.7v 1.3v 0.3v gnd 3v t r c l = 6ns t f c l = 6ns 1.3v 1.3v t wl t wh 0.3v t wl + t wh = fc l i t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90% t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
8 figure 7. hc three-state propagation delay waveform figure 8. hct three-state propagation delay waveform note: open drain waveforms t plz and t pzl are the same as those for three-state shown on the left. the test circuit is output r l =1k ? to v cc , c l = 50pf. figure 9. hc and hct three-state propagation delay test circuit test circuits and waveforms (continued) 50% 10% 90% gn d v cc 10% 90% 50% 50% output disable output low to off o utput high to off outputs enabled outputs disabled outputs enabled 6ns 6ns t pzh t phz t pzl t plz 0.3 2.7 gn d 3v 10% 90% 1.3v 1.3v output disable output low to off o utput high to off outputs enabled outputs disabled outputs enabled t r 6ns t pzh t phz t pzl t plz 6ns t f 1.3 ic with three- state output other inputs t ied high or low output disable v cc for t plz and t pzl gnd for t phz and t pz h output r l = 1k ? c l 50pf cd54hc670, cd74hc670, CD74HCT670 cd54hc670, cd74hc670, CD74HCT670
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) cd54hc670f3a active cdip j 16 1 tbd call ti level-nc-nc-nc cd74hc670e active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc670ee4 active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc cd74hc670m active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc670m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc670m96e4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc670me4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc670mt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc670mte4 active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670e active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc CD74HCT670ee4 active pdip n 16 25 pb-free (rohs) cu nipdau level-nc-nc-nc CD74HCT670m active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670m96 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670m96e4 active soic d 16 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670me4 active soic d 16 40 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670mt active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim CD74HCT670mte4 active soic d 16 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder package option addendum www.ti.com 26-sep-2005 addendum-page 1
temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 26-sep-2005 addendum-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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